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2005 Microchip Technology Inc.
Preliminary
DS41265A-page 199
PIC16F946
ADCON0
1Fh
0000 0000
uuuu uuuu
OPTION_REG
81h/181h
1111 1111
uuuu uuuu
TRISA
85h
1111 1111
uuuu uuuu
TRISB
86h/186h
1111 1111
uuuu uuuu
TRISC
87h
1111 1111
uuuu uuuu
TRISD
88h
1111 1111
uuuu uuuu
TRISE
89h
1111 1111
uuuu uuuu
PIE1
8Ch
0000 0000
uuuu uuuu
PIE2
8Dh
0000 0000
uuuu uuuu
PCON
8Eh
--01 --0x
--0u --uu
(1,5)
--uu --uu
OSCCON
8Fh
-110 q000
-110 x000
-uuu uuuu
OSCTUNE
90h
---0 0000
---u uuuu
ANSEL
91h
1111 1111
uuuu uuuu
PR2
92h
1111 1111
SSPADD
93h
0000 0000
uuuu uuuu
SSPSTAT
94h
0000 0000
uuuu uuuu
WPUB
95h
1111 1111
uuuu uuuu
IOCB
96h
0000 ----
uuuu ----
CMCON1
97h
---- --10
---- --uu
TXSTA
98h
0000 -010
uuuu -uuu
SPBRG
99h
0000 0000
uuuu uuuu
CMCON0
9Ch
0000 0000
uuuu uuuu
VRCON
9Dh
0-0- 0000
u-u- uuuu
ADRESL
9Eh
xxxx xxxx
uuuu uuuu
ADCON1
9Fh
-000 ----
-uuu ----
WDTCON
105h
---0 1000
---u uuuu
LCDCON
107h
0001 0011
uuuu uuuu
LCDPS
108h
0000 0000
uuuu uuuu
LVDCON
109h
--00 -100
--uu -uuu
EEDATL
10Ch
0000 0000
uuuu uuuu
EEADRL
10Dh
0000 0000
uuuu uuuu
EEDATH
10Eh
--00 0000
0000 0000
uuuu uuuu
EEADRH
10Fh
---0 0000
0000 0000
uuuu uuuu
LCDDATA0
110h
xxxx xxxx
uuuu uuuu
LCDDATA1
111h
xxxx xxxx
uuuu uuuu
LCDDATA2
112h
xxxx xxxx
uuuu uuuu
TABLE 16-4:
INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)
Register
Address
Power-on
Reset
MCLR Reset
WDT Reset
Brown-out Reset(1)
Wake-up from Sleep
through interrupt
Wake-up from Sleep
through WDT time-out
Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition.
Note 1:
If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.
2:
One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).
3:
When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt
vector (0004h).
4:
See Table 16-5 for Reset value for specific condition.
5:
If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.
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